Prof. Dr.-Ing. Thilo Pionteck

Prof. Dr.-Ing. Thilo Pionteck

Institut für Informations- und Kommunikationstechnik (IIKT)
Chair of Hardware-oriented technical Computer Science
Universitätsplatz 2, 39106 Magdeburg, G03-301   vCard
Projects

Current projects

Technology-aware 3D Interconnect Architectures for heterogeneous SoCs manufactured in Monolithic 3D Integration
Duration: 01.11.2022 bis 31.10.2025

Monolithic 3D integration (M3D) is a disruptive technology for the design of 3D System-on-Chips. In contrast to more conventional 3D integration schemes, M3D permits a very dense integration of vertical interconnects between neighboring tiers. Together with extrinsic heterogeneity, i.e., the combination of tiers with different electrical characteristics, unprecedented opportunities for new architectural designs and extended system functionalities arise.
These benefits have been proven by numerous works addressing processing elements and memories; yet, for on-chip communication architectures such as Network-on-Chips, only few related works exist. Further on, these works often neglect the significant impact of intrinsic heterogeneity caused by monolithic fabrication, such as process-related transistor degradations on higher tiers, interconnect degradations on lower tiers, or the non-uniform distribution of routing resources among tiers. Finally, previous works primarily exploit wire length reduction in 3D, yet do not consider the extended micro- and macroarchitectural design space.
We want to address all of these shortcomings by analyzing how the characteristics of monolithic 3D integration affect the design of the microarchitecture of individual network components, and the architecture of the communication infrastructure. Furthermore, we will analyze the impact of these modifications and extended design options on the overall system architecture.
The project will provide four specific contributions to the scientific community:
1) It will provide systematic design guidelines and a set of architectural templates for optimized 3D interconnect architectures addressing extrinsic and intrinsic heterogeneity;
2) it will provide models for formulating Network-on-Chip topology synthesis as an optimization problem;
3) it will provide a toolset for supporting a systematic design space exploration, which accounts for all relevant M3D technology characteristics;
4) it will demonstrate the optimization potential by means of two demonstrators, a Vision-System-on-Chip and a multiprocessor system.

The main outcome of this project will be a deeper understanding on how the disruptive characteristics of Monolithic 3D integration can be exploited for improving the interconnect architecture in 3D integrated circuits. This allows for the design of optimized systems, not supported by current design concepts.

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Hybrid^2-Index Structures for Main Memory Databases
Duration: 01.01.2020 bis 31.12.2024

Aim of this project is to speed up index accesses of database management systems (DBMS) in order to improve the total performance. As index accesses are starting points for all succeeding processing steps of database queries, fast index accesses are the key to a superior total performance of DBMS. For the purpose of speeding up index accesses we propose to investigate and develop new hardware-/software index structures, which realize structure-hybrid indexes, i.e., the combination of static and dynamic indexes, on hybrid shared-memory system architectures consisting of a CPU and an FPGA or GPU as hardware accelerator. Such hybrid^2-indexes are not considered so far in literature, such that the possibilities of current hybrid shared-memory system architectures are not utilized in an optimal way. Because of the reduction of the communication costs between CPU and hardware accelerator many existing design rules for utilizing hardware accelerators must be rethought, especially concerning the complexities of tasks taken over by the hardware accelerators.Within this project we will hence research on which and how static and dynamic index structures can be realized in an efficient way with high performance on hybrid systems. Furthermore, we will investigate how to react on changing access patterns by dynamically swapping used index structures on the hardware accelerators. We expect novel, adaptive structure- and hardware-hybrid index structures, which significantly improve the performance of index accesses in DBMS in comparison to existing traditional systems.

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ADAMANT-II: Adaptive Data Management in Evolving Heterogeneous Hardware/Software Systems
Duration: 01.06.2021 bis 31.05.2024

Heterogeneous system architectures consisting of CPUs, GPUs and FPGAs offer a variety of optimization possibilities for database systems compared to pure CPU-based systems. However, it has been shown that it is not sufficient to just map existing software concepts one-to-one to non von-Neumann hardware architectures such as FPGAs to fully exploit their optimization potential. Rather, new processing capabilities require the design of novel processing concepts, which have to be considered at the planning level of query processing. A basic processing concept has already been developed in the first project phase by considering device-specific features in our plug’n’play system architecture. In fact, more advanced concepts are required to achieve an optimal exploitation of the capabilities of the hardware architectures. While significant speed-ups were achieved on the level of individual operators mapped to GPUs and FPGAs, the performance gain at the level of complete queries was unsatisfying. Hence, we derived the hypothesis for the second project phase that standard query-mapping approaches with their consideration of queries on the level of individual operators is not sufficient to explore the extended processing features of heterogeneous system architectures.
We will address this shortcoming by researching new processing and query mapping methods for heterogeneous systems, which question the commonly used granularity level of operators. Therefore, we will provide processing entities that encapsulate a greater functionality than standard database operators and may span multiple hardware devices. Thus, processing entities are intrinsically heterogeneous and combine the specific features of individual devices. As a result, our heterogeneous system architecture enables database operations and features that are not available or cannot be implemented efficiently in classical database systems.
To explore this extended feature set, we have identified three application domains that are still challenging for classical database systems and for which we assume that they will benefit greatly from heterogeneous system architectures: High-volume data feeds, approximate query processing and dynamic multi-query processing. The stream-based nature of high-volume data feeds asks for a hardware architecture where processing can be done on the fly without the need to store data beforehand. Hence, FPGAs are a promising hardware platform for processing high-volume data feed applications. Furthermore, FPGAs as well as GPUs are good platforms for approximate query processing, as they allow for approximate arithmetics and hardware-influenced sampling techniques. Dynamic multi-query processing is very challenging from the system management point of view, as query plans that have performed well for one workload can be inefficient for a different workload. Here, the multi-level parallelism of heterogeneous systems offers better opportunities to handle heavy workloads.

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Completed projects

Our aim is to develop new processing concepts for exploiting the special characteristics of hardware accelerators in heterogeneous system architectures for classical and non-classical database systems. On the system management level, we want to research alternative query modeling concepts and mapping approaches that are better suited to capture the extended feature sets of heterogeneous hardware/software systems. On the hardware level, we will work on how processing engines for non-classical database systems can benefit from heterogeneous hardware and in which way processing engines mapped across device boundaries may provide benefits for query optimization. Our working hypothesis is that standard query mapping approaches with their consideration of queries on the level of individual operators is not sufficient to explore the extended processing features of heterogeneous system architectures. In the same way, implementing a complete operator on an individual device does not seem to be optimal to exploit heterogeneous systems. We base these claims on our results from the first project phase where we developed the ADAMANT architecture allowing a plug & play integration of heterogeneous hardware accelerators. We will extend ADAMANT by the proposed processing approaches in the second project phase and focus on how to utilize the extended feature sets of heterogeneous systems rather than how to set such systems up.
Duration: 01.01.2021 bis 31.12.2023

Heterogene Systemarchitekturen bestehend aus CPUs, GPUs und FPGAs bieten vielfältige Optimierungsmöglichkeiten im Vergleich zu rein CPU-basierten Systemen. Zur vollständigen Ausnutzung dieses Optimierungspotenzials reicht es jedoch nicht, bestehende Softwarekonzepte unverändert auf nicht-von-Neumann-Architekturen wie beispielsweise FPGAs zu übertragen. Vielmehr erfordern die zusätzlichen Verarbeitungsmöglichkeiten dieser Architekturen den Entwurf neuartiger Verarbeitungskonzepte. Dies ist bereits in der Planung der Anfrageverarbeitung zu berücksichtigen. In der ersten Projektphase entwickelten wir hierfür bereits ein erstes Konzept, welches die gerätespezifischen Merkmale in unserer Plug’n’Play Architektur berücksichtigt. Allerdings sehen wir die Notwendigkeit zu dessen Weiterentwicklung, um eine noch bessere Ausnutzung der spezifischen Eigenschaften der Hardwarearchitekturen zu erreichen. Für die zweite Projektphase stellen wir daher die Hypothese auf, dass bekannte Verfahren zur Abbildung von Anfragen auf der Ebene einzelner Operatoren nicht ausreichen sind, um die erweiterten Verarbeitungsmöglichkeiten heterogener Systemarchitekturen auszunutzen.
Unser Ziel ist daher die Erforschung neuartiger Verarbeitungskonzepte und Verfahren zur Abbildung von Anfragen für heterogene Systeme, welche von der üblicherweise verwendeten Granularität auf Ebene einzelner Operatoren abweichen. Wir werden Verarbeitungseinheiten entwickeln, die eine größere Funktionalität als einzelne Operatoren bereitstellen und sich über mehrere Geräte hinweg erstrecken. Diese Verarbeitungseinheiten sind in sich heterogen und kombinieren die spezifischen Eigenschaften einzelner Architekturen. Im Ergebnis ermöglicht unsere heterogene Systemarchitektur das Bereitstellen von Datenbankoperationen und Funktionen, die in klassischen Datenbanksystemen nicht verfügbar oder nicht effizient realisierbar sind.
Zu Demonstrationszwecken haben wir drei Anwendungsfälle identifiziert, welche von heterogenen Systemarchitekturen stark profitieren können: Verarbeitung von Datenströmen mit hohem Aufkommen, approximative Anfrageverarbeitung und dynamische Multianfrageverarbeitung. Hochvolumige Datenströme erfordern eine Hardwarearchitektur, die eine Verarbeitung der Daten ohne vorherige Zwischenspeicherung ermöglicht. Dafür stellen FPGAs eine vielversprechende Plattform durch ihr datenstrombasiertes Verarbeitungsprinzip dar. Darüber hinaus eignen sich sowohl FPGAs als auch GPUs für approximierende Anfragenverarbeitungen, da sie arithmetische Operationen mit reduzierter Genauigkeit und die Realisierung von approximativen, hardwarebeschleunigten Samplingtechniken ermöglichen. Die dynamische Multianfrageverarbeitung ist aus Systemsicht sehr anspruchsvoll, da variable Systemlasten die Effizienz zuvor aufgestellter Anfragepläne reduzieren können. Hier ermöglichen die zahlreichen Parallelitätsebenen in heterogenen Systemen eine bessere Verteilung der Systemlasten.

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Adaptive Data Management in Evolving Heterogeneous Hardware/Software Systems
Duration: 01.09.2017 bis 31.10.2022

Currently, database systems face two big challenges: First, the application scenarios become more and more diverse ranging from purely relational to graph-shaped or stream-based data analysis. Second, the hardware landscape becomes more and more heterogeneous with standard multi-core Central Processing Units (CPUs) as well as specialized high-performance co-processors such as Graphics Processing Unit (GPUs) or Field Programmable Gate Arrays (FPGAs).
Recent research shows that operators designed for co-processors can outperform their CPU counterparts. However, most of the approaches focus on single-device processing to speedup single analyses not considering overall system performance. Consequently, they miss hidden performance potentials of parallel processing across all devices available in the system. Furthermore, current research results are hard to generalize and, thus, cannot be applied to other domains and devices.
In this project, we aim to provide integration concepts for diverse operators and heterogeneous hardware devices in adaptive database systems. We work on optimization strategies not only exploiting individual device-specific features but also the inherent cross-device parallelism in multi-device systems. Thereby we focus on operators from the relational and graph domain to derive concepts not limited to a certain application domain. To achieve the project goals, interfaces and abstraction concepts for operators and processing devices have to be defined. Furthermore, operator and device characteristics have to be made available to all system layers such that the software layer can account for device specific features and the hardware layer can adapt to the characteristics of the operators and data. The availability of device and operator characteristics is especially important for global query optimization to find a suitable execution strategy. Therefore, we also need to analyze the design space for query processing on heterogeneous hardware, in particular with regards to functional, data and cross-device parallelism. To handle the enormous complexity of the query optimization design space incurred by the parallelism, we follow a distributed optimization approach where optimization tasks are delegated to the lowest possible system layer. Lower layers also have a more precise view on device-specific features allowing to exploit them more efficiently. To avoid interferences of optimization decisions at different layers, a focus is also set on cross-layer optimizations strategies. These will incorporate learning-based techniques for evaluating optimization decisions at runtime to improve future optimization decisions. Moreover, we expect that learning-based strategies are best suited to integrate device-specific features not accounted for by the initial system design, such as it is often the case with the dynamic partial reconfiguration capabilities of FPGAs.

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Joint research projekt: Research and development of a freely configurable, open and dose-saving computer tomograph (KIDs-CT) - Sub-project:; Processing of detector signals
Duration: 01.10.2017 bis 31.03.2021

We design an open-source system that reads the detector data in computer tomography, hierarchically aggregates these, and calculates signal (pre-) processing. The system consists of industry-standard components. It is the first CT-scanner with open-source interfaces and publically available system architecture. This opens unparalleled potential for research and optimization: The (pre-) processing of raw data in close proximity to the signal source increases the signal quality. The amount of data send in the communication is reduced. The combination of (pre-) processing and subsequent algorithms for image reconstruction sharply increases the image quality.

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Technology-aware Asymmetric 3D-Inteconnect Architectures: Templates and Design Methods
Duration: 01.07.2017 bis 31.12.2020

New production methods enable the design of heterogeneous 3D-System-on-Chips (3D-SoCs), which consist of stacked silicon dies manufactured with different technologies. In contrast to homogeneous SoCs, this allows to adjust the technological characteristics of each die to the specific requirements of the components placed in each layer. Heterogeneous 3D-SoCs provide unprecedented integration possibilities for embedded and high performance systems. To exploit that potential, powerful, flexible, and scalable communication infrastructures are required. Yet, current interconnect architectures (IAs) tacitly assume a multilayer homogeneous 3D-SoC and do not consider the influence of different technology parameters on the topology, architectural, and micro-architectural level of the IA.

In this project, we aim to develop architectural templates and design methods for 3D-interconnect architectures for heterogeneous 3D-SoCs. We target two main innovations: First, we will exploit the specific technology characteristics of individual chip layers in heterogeneous 3D-SoCs. Therefore, we will re-evaluate and extend existing approaches for heterogeneous and hybrid 2D-interconnect architectures. Second, we aim at discovering
new interaction mechanisms among components, which may be spatially distributed even at the micro-architectural level, to exploit their diverse features when manufactured in different technologies. The combination of these aspects leads to technology asymmetric 3D-interconnect architectures (TA-3D-IAs), as defined in this proposal for the first time.

The main outcome of the project will be a deeper understanding of TA-3D-IAs as part of heterogeneous 3D-SoCs. Further, we will develop systematic design methodologies and a set of architectural templates for the design of TA-3D-IAs. Therefor we will create a full-fledged simulation framework for the analysis of TA-3D-IAs' design space, which will be capable of accounting for technology-specific parameters for all components of the communication infrastructure. In addition, we will provide reference benchmarks and selected TA-3D-IAs, which will allow other research teams to evaluate and compare their ideas.

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Hardware-acceleration of Semantic Web databases with runtime reconfigurable FPGAs
Duration: 01.10.2014 bis 30.06.2017

The relevance of the Semantic Web has been increased steadily over the recent years. This can be shown by the increasing number of developed and used Semantic Web tools and applications.The main idea of the Semantic Web is to consider the semantic of symbols to enable a more precise machine processing. For this purpose, the necessary links between data sets are stored in database systems. The continuously increasing size of the data sets leads to performance issues for traditional databases and even specialized Semantic Web databases. In the scope of Semantic Web databases data sets with billions of entries are available and processing of these data sets on software-based solutions is highly time consuming.Thus, in this project a hardware/software system will be investigated and developed to outsource time consuming tasks to a programmable logic chip (FPGA, Field Programmable Gate Array). The hardware acceleration of cost intensive tasks will cover the index generation as well as query processing in Semantic Web databases. During query processing the determination of which function should be mapped to the FPGA will be decided at runtime. As the mapping of the data path to the basic elements uses partial runtime reconfiguration, an optimal hardware accelerator can be provided for any query.

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Detection and adaptive prioritization of semi-static data streams and traffic patterns in Network-on-Chips
Duration: 01.04.2014 bis 31.12.2016

Aim of this project is the design and implementation of a traffic adaptive network-on-chip for communication latency reduction in complex manycore systems. Temporally constant communication patterns between functional units should be detected online and the corresponding data streams should be transferred without any delay by bypassing the complete router pipeline. Such temporally constant patterns exist for the duration of an application in multifunctional systems as well as temporally in manycore processor systems with distributed caches. Prioritization of suitable data streams will be applied to individual semi-static data streams between two functional units, as well as to repeating patterns of semi-static data streams. Traffic pattern detection is done locally by each router and only accounts the local routing decisions for all data streams of one router input. This allows local aggregation of several individual data streams with different destination addresses and virtual channel identifiers. If several consecutive routers prioritize the same aggregate, a direct point-to-point connection is set up. Depending on the actual traffic patterns this results in a combination of a packet-oriented and a circuit switched network-on-chip.The frequency of occurrence, duration and pattern of semi-static data streams do not only depend on the communication characteristics between functional blocks and their location, but also on the routing algorithm used. Therefore the effect of different deterministic and adaptive routing algorithms on these parameters needs to be evaluated. It is also intended to use adaptive routing algorithms to support the formation of aggregates of semi-static data streams. Adaptive and fault-tolerant routing algorithms will also be used to limit the effects of blocked networks links for non-prioritized data streams due to their exclusive use for semi-static data streams. Non-prioritized data streams need to be rerouted in such a way that prioritized connections can be sustained as long as possible. The network-on-chip architecture is dedicated for the use in ASIC designs as well as in partially reconfigurable FPGA designs. Performance, energy consumption and hardware requirements will be evaluated for both design alternatives. At the end of the project, the effectiveness of the network-on-chip architecture will be demonstrated by means of an FPGA-based test system.

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Publications

2024

Book chapter

Large filter low-level processing by edge TPU

Krell, Gerald; Pionteck, Thilo

In: Proceedings of the 19th International Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications. Volume 4 - Setubal : Scitepress Digital Library ; Radeva, Petia . - 2024, S. 464-473 [Konferenz: 19th International Joint Conference on Computer Vision, Imaging and Computer Graphics Theory and Applications, Rome,Italy, February 27-29, 2024]

2023

Book chapter

A flexible and scalable reconfigurable FPGA overlay architecture for data-flow processing

Drewes, Anna; Burtsev, Vitalii; Gurumurthy, Balasubramanian; Wilhelm, Martin; Bronske, David; Saake, Gunter; Pionteck, Thilo

In: 31st IEEE International Symposium on Field-Programmable Custom Computing Machines , 2023 - Piscataway, NJ : IEEE ; Prasanna, Viktor, S. 212

Book chapter

Modeling task mapping for data-intensive applications in heterogeneous systems

Wilhelm, Martin; Geppert, Hanna; Drewes, Anna; Pionteck, Thilo

In: Euro-Par 2022: Parallel Processing Workshops , 1st ed. 2023. - Cham : Springer Nature Switzerland ; Singer, Jeremy, S. 145-157 - (Lecture notes in computer science; volume 13835)

Book chapter

ADAMANT - a query executor with plug-in interfaces for easy co-processor integration

Gurumurthy, Balasubramanian; Broneske, David; Durand, Gabriel Campero; Pionteck, Thilo; Saake, Gunter

In: 2023 IEEE 39th International Conference on Data Engineering workshops - Piscataway, NJ : IEEE, S. 1153-1166

Book chapter

FPGA-integrated bag of little bootstraps accelerator for approximate database query processing

Burtsev, Vitalii; Wilhelm, Martin; Drewes, Anna; Gurumurthy, Balasubramanian; Broneske, David; Pionteck, Thilo; Saake, Gunter

In: Applied Reconfigurable Computing. Architectures, Tools, and Applications , 1st ed. 2023. - Cham : Springer Nature Switzerland ; Palumbo, Francesca, S. 115-130 - ( Lecture notes in computer science; volume 14251)

Peer-reviewed journal article

Enabling plug-and-play in cyber-physical systems using MPSoC-FPGAs

Passaretti, Daniele; Steiger, Max; Pionteck, Thilo

In: IEEE access / Institute of Electrical and Electronics Engineers - New York, NY : IEEE, Bd. 11 (2023), S. 116219-116234

Peer-reviewed journal article

A comprehensive modeling approach for the task mapping problem in heterogeneous systems with dataflow processing units

Wilhelm, Martin; Geppert, Hanna; Drewes, Anna; Pionteck, Thilo

In: Concurrency and computation - Chichester : Wiley, Bd. 35 (2023), Heft 25, Artikel e7909, insges. 24 S.

Peer-reviewed journal article

Hybrid CPU/GPU/APU accelerated query, insert, update and erase operations in hash tables with string keys

Groth, Tobias; Groppe, Sven; Pionteck, Thilo; Valdiek, Franz; Koppehel, Martin

In: Knowledge and information systems - London : Springer . - 2023, insges. 19 S.

Peer-reviewed journal article

Novel insights on atomic synchronization for sort-based group-by on GPUs

Gurumurthy, Bala; Broneske, David; Schäler, Martin; Pionteck, Thilo; Saake, Gunter

In: Distributed and parallel databases - New York, NY [u.a.] : Consultants Bureau . - 2023, insges. 23 S.

Editor

Architecture of Computing Systems - 36th International Conference, ARCS 2023, Athens, Greece, June 13–15, 2023, Proceedings

Goumas, Georgios; Tomforde, Sven; Brehm, Jürgen; Wildermann, Stefan; Pionteck, Thilo

In: Cham: Imprint: Springer, 2023., 1 Online-Ressource(XIX, 328 p. 125 illus., 91 illus. in color.) - (Lecture Notes in Computer Science; 13949), ISBN: 978-3-031-42785-5

2022

Book chapter

Accelerated parallel hybrid GPU/CPU hash table queries with string keys

Groth, Tobias; Groppe, Sven; Pionteck, Thilo; Valdiek, Franz; Koppehel, Martin

In: Konferenz: 33rd International Conference on Database and Expert Systems Applications, DEXA 2022, Vienna, Austria, August 22-24, 2022, Database and Expert Systems Applications - Cham: Springer International Publishing; Strauss, Christine . - 2022, S. 191-203 - (Lecture notes in computer science; volume 13427)

Book chapter

Dead-ends in FPGAs for database acceleration

Drewes, Anna; Koppehel, Martin; Pionteck, Thilo

In: Konferenz: 21st International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, SAMOS 2021, virtual event, July 4-8, 2021, Embedded Computer Systems: Architectures, Modeling, and Simulation - Cham: Springer International Publishing; Orailoglu, Alex . - 2022, S. 493-504 - (Lecture notes in computer science; volume 13227)

Book chapter

Hardware isolation support for low-cost SoC-FPGAs

Passaretti, Daniele; Boehm, Felix; Wilhelm, Martin; Pionteck, Thilo

In: Konferenz: International Conference on Architecture of Computing Systems, ARCS 2022, Heilbronn, Germany, September 13-15, 2022, Architecture of computing systems - 35th International Conference, ARCS 2022, Heilbronn, Germany, September 13-15, 2022 : proceedings - Cham: Springer; Schulz, Martin . - 2022, S. 148-163 - (Lecture notes in computer science; volume 13642)

Peer-reviewed journal article

Hardware optimizations of the X-ray pre-processing for interventional computed tomography using the FPGA

Passaretti, Daniele; Ghosh, Mukesh; Abdurahman, Shiras; Egito, Micaela Lambru; Pionteck, Thilo

In: Applied Sciences - Basel: MDPI, Bd. 12 (2022), 11, insges. 24 S.

Editor

Architecture of computing systems - 35th International Conference, ARCS 2022, Heilbronn, Germany, September 13-15, 2022 : proceedings

Papadopoulou, Nikela; Pionteck, Thilo; Schulz, Martin; Trinitis, Carsten

In: Cham: Springer, 2022, 1 Online-Ressource - (Lecture notes in computer science; volume 13642), ISBN: 978-3-031-21867-5

Scientific monograph

3D Interconnect Architectures for Heterogeneous Technologies - Modeling and Optimization

Bamberg, Lennart; Joseph, Jan Moritz; García-Ortiz, Alberto; Pionteck, Thilo

In: Cham: Imprint: Springer, 2022., 1st ed. 2022., 1 Online-Ressource(XXV, 395 p. 102 illus., 100 illus. in color.) - (Springer eBook Collection)

2021

Book chapter

Ultra-low-latency video encoding on heterogenous hardware platforms

Koppehel, Martin; Pionteck, Thilo

In: 2020 International Conference on Field-Programmable Technology - Piscataway, NJ: IEEE . - 2021, S. 287

Book chapter

An investigation of atomic synchronization for sort-based group-by aggregation on GPUs

Gurumurthy, Bala; Broneske, David; Schäler, Martin; Pionteck, Thilo; Saake, Gunter

In: 2021 IEEE 37th International Conference on Data Engineering workshops / IEEE International Conference on Data Engineering , 2021 - Piscataway, NJ : IEEE, S. 48-53

Book chapter

StreamGrid - an AXI-stream-compliant overlay architecture

Blochwitz, Christopher; Philipp, León; Bereković, Mladen; Pionteck, Thilo

In: Symposium: 17th International Symposium, ARC 2021, Virtual Event, June 2930, 2021, Applied Reconfigurable Computing. Architectures, Tools, and Applications/ ARC - Cham: Springer International Publishing; Derrien, Steven . - 2021, S. 156-170 - ( Lecture notes in computer science; volume 12700)

Book chapter

Architecture, dataflow and physical design implications of 3D-ICs for DNN-accelerators

Joseph, Jan Moritz; Samajdar, Ananda; Zhu, Lingjun; Leupers, Rainer; Lim, Sung Kyu; Pionteck, Thilo; Krishna, Tushar

In: Proceedings of the Twenty Second International Symposium on Quality Electronic Design/ ISQED - [Piscataway, NJ]: IEEE; Ghosh, Swaroop . - 2021, S. 60-66

Book chapter

Bridging the frequency gap in heterogeneous 3D SoCs through technology-specific NoC router architectures

Jeong, Geonhwa; Chien, Ruei-Ting; Leupers, Rainer; Garía-Ortiz, Alberto; Krishna, Tushar; Pionteck, Thilo

In: Proceedings of the 26th Asia and South Pacific Design Automation Conference - New York,NY,United States: Association for Computing Machinery . - 2021, S. 197-203

Book chapter

CuART - a CUDA-based, scalable Radix-Tree lookup and update engine

Koppehel, Martin; Groth, Tobias; Groppe, Sven; Pionteck, Thilo

In: Konferenz: 50th International Conference on Parallel Processing, ICPP 2021, Lemont, Il, USA, August 9 - 12, 2021, 50th International Conference on Parallel Processing - New York,NY,United States: Association for Computing Machinery . - 2021, insges. 10 S.

Book chapter

Configurable pipelined datapath for data acquisition in interventional computed tomography

Passaretti, Daniele; Pionteck, Thilo

In: 29th IEEE International Symposium on Field-Programmable Custom Computing Machines/ IEEE International Symposium on Field-Programmable Custom Computing Machines - Piscataway, NJ: IEEE; Bobda, Christophe . - 2021, S. 257

Peer-reviewed journal article

In-depth analysis of OLAP query performance on heterogeneous hardware

Broneske, David; Drewes, Anna; Gurumurthy, Bala; Hajjar, Imad; Pionteck, Thilo; Saake, Gunter

In: Datenbank-Spektrum - Berlin : Springer, Bd. 21 (2021), S. 133-143

Peer-reviewed journal article

Ratatoskr - an open-source framework for in-depth power, performance, and area analysis and optimization in 3D NoCs

Joseph, Jan Moritz; Bamberg, Lennart; Hajjar, Imad; Perjikolaei, Behnam Razi; García-Ortiz, Alberto; Pionteck, Thilo

In: ACM transactions on modeling and computer simulation/ Association for Computing Machinery - New York, NY: ACM Press, Bd. 32 (2021), 1, insges. 21 S.

Editor

Architecture of Computing Systems - 34th International Conference, ARCS 2021, Virtual Event, June 78, 2021, Proceedings

Hochberger, Christian; Bauer, Lars; Pionteck, Thilo

In: Cham: Imprint: Springer, 2021., 1st ed. 2021., 1 Online-Ressource(XVIII, 229 p. 81 illus., 67 illus. in color.) - (Springer eBook Collection; Theoretical Computer Science and General Issues; 12800)

2020

Book chapter

He..ro DB - a concept for parallel data processing on heterogeneous hardware

Müller, Michael; Leich, Thomas; Pionteck, Thilo; Saake, Gunter; Teubner, Jens; Spinczyk, Olaf

In: Architecture of Computing Systems ARCS 2020 - 33rd International Conference, Aachen, Germany, May 2528, 2020, Proceedings: 33rd International Conference, Aachen, Germany, May 2528, 2020, Proceedings - Cham: Springer International Publishing; Brinkmann, André. . - 2020, S. 82-96 - ( Lecture notes in computer science; 12155)

Book chapter

Optimising operator sets for analytical database processing on FPGAs

Drewes, Anna; Joseph, Jan Moritz; Gurumurthy, Balasubramanian; Broneske, David; Saake, Gunter; Pionteck, Thilo

In: Applied Reconfigurable Computing. Architectures, Tools, and Applications: 16th International Symposium, ARC 2020, Toledo, Spain, April 13, 2020, Proceedings - Cham: Springer International Publishing . - 2020, S. 30-44 - (Lecture Notes in Computer Science; volume 12083)

Book chapter

Ultra-low-latency video encoding on heterogenous hardware platforms

Koppehel, Martin; Pionteck, Thilo

In: 2020 International Conference on Field-Programmable Technology/ International Conference on Field-Programmable Technology - Piscataway, NJ: IEEE; Lin, Mingjie . - 2020, S. 287

Book chapter

Parallelizing approximate search on adaptive radix trees

Groth, Tobias; Groppe, Sven; Koppehel, Martin; Pionteck, Thilo

In: CEUR workshop proceedings - Aachen, Germany: RWTH Aachen, Bd. 2646 (2020), S. 56-67

Book chapter

Hardware/Software Co-Design of a control and data acquisition system for Computed Tomography

Passaretti, Daniele; Pionteck, Thilo

In: 2020 9th International Conference on Modern Circuits and Systems Technologies (MOCAST)/ MOCAST - [Piscataway, NJ]: IEEE . - 2020, insges. 4 S.

Peer-reviewed journal article

Application-specific SoC design using core mapping to 3D mesh NoCs with nonlinear area optimization and simulated annealing

Joseph, Jan Moritz; Ermel, Dominik; Bamberg, Lennart; García-Oritz, Alberto; Pionteck, Thilo

In: Technologies: open access journal - Basel: MDPI, Bd. 8 (2020), 1, insges. 10 S.

Editor

Architecture of Computing Systems – ARCS 2020 - 33rd International Conference, Aachen, Germany, May 25–28, 2020, Proceedings

Brinkmann, André.; Karl, Wolfgang; Lankes, Stefan; Tomforde, Sven; Pionteck, Thilo; Trinitis, Carsten

In: Cham: Imprint: Springer, 2020., 1 Online-Ressource(XII, 257 p. 112 illus., 62 illus. in color.) - (Theoretical Computer Science and General Issues; 12155; Springer eBook Collection), ISBN: 978-3-030-52794-5

Article in conference proceedings

When vectorwise meets hyper, pipeline breakers become the moderator

Gurumurthy, Balasubramanian; Hajjar, Imad; Broneske, David; Pionteck, Thilo; Saake, Gunter

In: ADMS 2020: eleventh International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures : Monday, August 31, 2020 : in conjunction with VLDB 2020 - Tokyo . - 2020

2019

Abstract

Computed tomography hardware architectural model FPGA-based

Passaretti, Daniele; Pionteck, Thilo

In: 4th Image-Guided Interventions Conference: digitalization in medicine : November 4th-5th 2019, UMM, Mannheim - Mannheim, 2019 . - 2019

Book chapter

System-level optimization of network-on-chips for heterogeneous 3D system-on-chips

Joseph, Jan Moritz; Ermel, Dominik; Bamberg, Lennart; García Oritz, Alberto; Pionteck, Thilo

In: Konferenz: IEEE 37th International Conference on Computer Design, ICCD, Abu Dhabi, United Arab Emirates, 17-20 November 2019, 2019 IEEE International Conference on Computer Design/ IEEE International Conference on Computer Design - Piscataway, NJ: IEEE . - 2019, S. 409-412

Book chapter

Survey on FPGAs in medical radiology applications - challenges, architectures and programming models

Passaretti, Daniele; Joseph, Jan Moritz; Pionteck, Thilo

In: Konferenz: International Conference on Field-Programmable Technology, ICFPT, Tianjin, China, 09-13 December 2019, 2019 International Conference on Field-Programmable Technology/ ICFPT - Piscataway, NJ: IEEE . - 2019, S. 279-282

Book chapter

Efficient inter-kernel communication for OpenCL database operators on FPGAs

Drewes, Anna; Joseph, Jan Moritz; Gurumurthy, Bala; Broneske, David; Saake, Gunter; Pionteck, Thilo

In: 2018 International Conference on Field-Programmable Technology (FPT) - [Piscataway, NJ]: IEEE, 2019[Konferenz: 2018 International Conference on Field-Programmable Technology, FPT, Naha, Okinawa, Japan, 10-14 December 2018]

Book chapter

Hardware-accelerated index construction for semantic web

Blochwitz, Christopher; Wolff, Julian; Bereković, Mladen; Heinrich, Dennis; Groppe, Sven; Joseph, Jan Moritz; Pionteck, Thilo

In: Konferenz: 2018 International Conference on Field-Programmable Technology, FPT, Naha, Okinawa, Japan, 10-14 December 2018, 2018 International Conference on Field-Programmable Technology/ International Conference on Field-Programmable Technology - Piscataway, NJ: IEEE . - 2019

Book chapter

Area optimization with non-linear models in core mapping for system-on-chips

Joseph, Jan Moritz; Ermel, Dominik; Drewes, Anna; Bamberg, Lennart; Garcia-Oritz, Alberto; Pionteck, Thilo

In: 2019 8th International Conference on Modern Circuits and Systems Technologies (MOCAST): May 13-15, 2019, Aristotle University Research Dissemination Center (KEDEA), Thessaloniki, Greece/ International Conference on Modern Circuits and Systems Technologies - [Piscataway, NJ]: IEEE . - 2019

Peer-reviewed journal article

Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment

Bamberg, Lennart; Joseph, Jan Moritz; Pionteck, Thilo; García Ortiz, Alberto

In: Integration, the VLSI journal - Amsterdam [u.a.]: Elsevier Science, 1983, Bd. 67.2019, S. 60-72

Peer-reviewed journal article

NoCs in heterogeneous 3D SoCs - co-design of routing strategies and microarchitectures

Joseph, Jan Moritz; Bamberg, Lennart; Ermel, Dominik; Perjikolaei, Behnam Razi; Drewes, Anna; García Ortiz, Alberto; Pionteck, Thilo

In: IEEE access/ Institute of Electrical and Electronics Engineers - New York, NY: IEEE, Bd. 7 (2019), S. 135145-135163

Peer-reviewed journal article

Simulation environment for link energy estimation in networks-on-chip with virtual channels

Joseph, Jan Moritz; Bamberg, Lennart; Hajjar, Imad; Schmidt, Robert; Pionteck, Thilo; García Ortiz, Alberto

In: Integration, the VLSI journal - Amsterdam [u.a.]: Elsevier Science, 1983 . - 2019[Online first]

Dissertation

Networks-on-Chip for heterogeneous 3D Systems-on-Chip

Joseph, Jan Moritz; Pionteck, Thilo

In: Magdeburg, 2019, xiv, 248 Seiten, Illustrationen, Diagramme, 30 cm[Literaturverzeichnis: Seite 235-246]

Editor

ARCS 2019 - 32nd GI/ITG International Conference on Architecture of Computing Systems : workshop proceedings : May 20-21, 2019, Technical University of Denmark, Copenhagen, Denmark

Trinitis, Carsten; Pionteck, Thilo

In: Berlin: VDE Verlag, 2019, 1 CD-ROM, 56 gKongress: GI/ITG International Conference on Architecture of Computing Systems 32 : Copenhagen$d2019.05.20-21

Editor

Architecture of Computing Systems ARCS 2019 - 32nd International Conference, Copenhagen, Denmark, May 2023, 2019, Proceedings

Schoeberl, Martin; Hochberger, Christian; Uhrig, Sascha; Brehm, Jürgen; Pionteck, Thilo

In: Cham: Springer, 2019, 1 Online-Ressource (XIX, 335 p. 212 illus., 88 illus. in color) - (Springer eBooks; Computer Science; Theoretical Computer Science and General Issues; 11479)

2018

Book chapter

Continuous live-tracing as debugging approach on FPGAs

Blochwitz, Christopher; Klink, Raphael; Joseph, Jan Moritz; Pionteck, Thilo

In: 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig17): Cancun, Mexico, December 4-6, 2017 - Piscataway, NJ: IEEE, insges. 8 S., 2018[Kongress: International Conference on Reconfigurable Computing and FPGAs, ReConFig17, Cancun, Mexico, December 4-6, 2017]

Book chapter

An FPGA-based prototyping framework for Networks-on-Chip

Drewes, Tobias; Joseph, Jan Moritz; Pionteck, Thilo

In: 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig17): Cancun, Mexico, December 4-6, 2017 - Piscataway, NJ: IEEE, insges. 7 S., 2018[Kongress: International Conference on Reconfigurable Computing and FPGAs, ReConFig17, Cancun, Mexico, December 4-6, 2017]

Book chapter

Coding-aware link energy estimation for 2D and 3D networks-on-chip with virtual channels

Bamberg, Lennart; Joseph, Jan Moritz; Schmidt, Robert; Pionteck, Thilo; García Ortiz, Alberto

In: 2018 IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS 2018): 2-4 July 2018, Spain/ IEEE International Symposium on Power and Timing Modeling, Optimization and Simulation - Piscataway, NJ: IEEE, 2018; IEEE International Symposium on Power and Timing Modeling, Optimization and Simulation (28.:2018) . - 2018, S. 222-228[Symposium: IEEE 28th International Symposium on Power and Timing Modeling, Optimization and Simulation, PATMOS 2018, Platja d'Aro, Spain, 2-4 July 2018]

Book chapter

Specification of simulation models for NoCs in heterogeneous 3D SoCs

Joseph, Jan Moritz; Bamberg, Lennart; Krell, Gerald; Hajjar, Imad; Garcia-Oritz, Alberto; Pionteck, Thilo

In: Proceedings of the 13th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC): July 9th-11th, 2018, Lille, France - Piscataway, NJ: IEEE, insges. 8 S.[Symposium: 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Lille, France, July 9th-11th, 2018]

Book chapter

Adaptive data processing in heterogeneous hardware systems

Gurumurthy, Balasubramanian; Drewes, Tobias; Broneske, David; Saake, Gunter; Pionteck, Thilo

In: CEUR workshop proceedings - Aachen: RWTH, Bd. 2126.2018, S. 10-15[Workshop: 30th GI-Workshop Grundlagen von Datenbanken, Wuppertal, Germany, May 22-25, 2018]

Book chapter

Search & update optimization of a B + tree in a hardware aided semantic web database system

Heinrich, Dennis; Werner, Stefan; Blochwitz, Christopher; Pionteck, Thilo; Groppe, Sven

In: Proceedings of the 7th International Conference on Emerging Databases - Singapore: Springer, S. 172-182, 2018 - (Lecture Notes in Electrical Engineering; 461)[Konferenz: 7th International Conference on Emerging Databases (EDB 2017), Busan, Korea, 7 - 9 August, 2017]

Book chapter

Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS

Joseph, Jan Moritz; Mey, Morten; Ehlers, Kristian; Blochwitz, Christopher; Winker, Tobias; Pionteck, Thilo

In: 2017 International Conference on Reconfigurable Computing and FPGAs (ReConFig17): Cancun, Mexico, December 4-6, 2017 - Piscataway, NJ: IEEE, insges. 8 S., 2018[Kongress: International Conference on Reconfigurable Computing and FPGAs, ReConFig17, Cancun, Mexico, December 4-6, 2017]

Peer-reviewed journal article

Hardware-aided update acceleration in a hybrid Semantic Web database system

Heinrich, Dennis; Werner, Stefan; Blochwitz, Christopher; Pionteck, Thilo; Groppe, Sven

In: The journal of supercomputing: an international journal of high-performance computer design, analysis and use - Dordrecht [u.a.]: Springer Science + Business Media B.V, insges. 24 S., 2018

Peer-reviewed journal article

Cooking DBMS operations using granular primitives - an overview on a primitive-based RDBMS query evaluation

Gurumurthy, Balasubramanian; Broneske, David; Drewes, Tobias; Pionteck, Thilo; Saake, Gunter

In: Datenbank-Spektrum - Berlin: Springer, Bd. 18.2018, 3, S. 183-193

Peer-reviewed journal article

Integration of FPGAs in database management systems - challenges and opportunities

Becher, Andreas; B.G., Lekshmi; Broneske, David; Drewes, Tobias; Gurumurthy, Balasubramanian; Meyer-Wegener, Klaus; Pionteck, Thilo; Saake, Gunter; Teich, Jürgen; Wildermann, Stefan

In: Datenbank-Spektrum - Berlin: Springer, Bd. 18.2018, 3, S. 145-156

Editor

ARCS 2018 - 31th International Conference on Architecture of Computing Systems April, 9-12, 2018, Technische Universität Braunschweig, Braunschweig, Germany, Workshop Proceedings

Trinitis, Carsten; Pionteck, Thilo

In: Berlin: VDE Verlag, 2018, CD-ROM, 12 cmKongress: GI/ITG International Conference on Architecture of Computing Systems 31 (Braunschweig : 2018.04.09-12)

Editor

Architecture of Computing Systems – ARCS 2018 - 31st International Conference, Braunschweig, Germany, April 9–12, 2018, Proceedings

Berekovic, Mladen; Buchty, Rainer; Hamann, Heiko; Koch, Dirk; Pionteck, Thilo

In: Cham: Springer, 2018, Online-Ressource (XV, 326 p. 112 illus, online resource) - (Lecture Notes in Computer Science; 10793; Theoretical Computer Science and General Issues; 10793; SpringerLink; Bücher; Springer eBook Collection; Computer Science), ISBN: 978-3-319-77610-1

2017

Book chapter

Design method for asymmetric 3D interconnect architectures with high level models

Joseph, Jan Moritz; Bamberg, Lennart; Wrieden, Sven; Ermel, Dominik; García-Oritz, Alberto; Pionteck, Thilo

In: 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017) : July 12-14, 2017, Madrid, Spain : proceedings - [Piscataway, NJ] : IEEE, insges. 8 S. [Symposium: 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2017, Madrid, Spain, July 12-14 2017]

Book chapter

An FPGA-based prototyping framework for networks-on-Chip

Drewes, Tobias; Joseph, Jan Moritz; Pionteck, Thilo

In: ReConFig'17 : 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ : IEEE [poster session A; Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig'17, Cancun, Mexico, December 4-6, 2017]

Book chapter

Hardware-accelerated radix-tree based string sorting for big data applications

Blochwitz, Christopher; Wolff, Julian; Joseph, Jan Moritz; Werner, Stefan; Heinrich, Dennis; Groppe, Sven; Pionteck, Thilo

In: Architecture of Computing Systems - ARCS 2017 - 30th International Conference, Vienna, Austria, April 36, 2017, Proceedings - Cham: Springer, 2017 . - 2017, S. 47-58 - (Lecture Notes in Computer Science; 10172)[Konferenz: 30th International Conference on Architecture of Computing Systems, ARCS 2017, Vienna, Austria, April 3-6, 2017]

Book chapter

Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS

Joseph, Jan Moritz; Mey, Morten; Ehlers, Kristian; Blochwitz, Christopher; Winker, Tobias; Pionteck, Thilo

In: ReConFig'17 : 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ : IEEE [Poster session B; Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig'17, Cancun, Mexico, December 4-6, 2017]

Book chapter

Contentious live-tracing as debugging approach on FPGAS

Blochwitz, Christopher; Klink, Raphael; Joseph, Jan Moritz; Pionteck, Thilo

In: ReConFig'17 : 2017 International Conference on Reconfigurable Computing and FPGAs : December 4-6, Cancun, Mexico - Piscataway, NJ : IEEE [General session; Konferenz: 2017 International Conference on Reconfigurable Computing and FPGAs, ReConFig'17, Cancun, Mexico, December 4-6, 2017]

Peer-reviewed journal article

Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs$Jan Moritz Joseph, ChristopherBlochwitz, Alberto García-Ortiz, Thilo Piontecka

Joseph, Jan Moritz; Blochwitz, Christopher; García Ortiz, Alberto; Pionteck, Thilo

In: Microprocessors and microsystems - Amsterdam [u.a.]: Elsevier, 1979, Bd. 48.2017, S. 36-47

Peer-reviewed journal article

Semi-static operator graphs for accelerated query execution on FPGAs

Werner, Stefan; Heinrich, Dennis; Groppe, Sven; Pionteck, Thilo

In: Microprocessors and microsystems - Amsterdam [u.a.] : Elsevier, 2017

Editor

ARCS 2017 - 30th International Conference on Architecture of Computing Systems : workshop proceedings : April, 3-6, 2017, Vienna University of Technology, Vienna, Austria

Trinitis, Carsten; Pionteck, Thilo

In: Offenbach: VDE Verlag GmbH, [2017], 1 CD-ROM, ISBN: 3800743957 Kongress: ARCS 30 Wien 2017

Editor

Architecture of Computing Systems - ARCS 2017 - 30th International Conference, Vienna, Austria, April 3–6, 2017, Proceedings

Knoop, Jens; Karl, Wolfgang; Schulz, Martin; Inoue, Kōji; Pionteck, Thilo

In: Cham: Springer, 2017, Online-Ressource (XIII, 262 p. 100 illus, online resource) - (Lecture Notes in Computer Science; 10172; SpringerLink; Bücher; Springer eBook Collection; Computer Science), ISBN: 978-3-319-54999-6

2016

Book chapter

A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip

Joseph, Jan Moritz; Wrieden, Sven; Blochwitz, Christopher; García Ortiz, Alberto; Pionteck, Thilo

In: 2016 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoc): June 27-29, 2016, Tallinn, Estonia - [Piscataway, NJ]: IEEE[Kongress: 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoc), 27. - 29.June 2016, Tallinn, Estonia]

Book chapter

Accelerated join evaluation in Semantic Web databases by using FPGAs

Werner, S.; Heinrich, D.; Stelzner, M.; Linnemann, V.; Pionteck, T.; Groppe, S.

In: Concurrency Computation, Vol. 28, 2016, Issue 7, S. 2031-2051, 10.1002/cpe.3502

Book chapter

An architectural template for composing application specific datapaths at runtime

Backasch, R.; Hempel, G.; Blochwitz, C.; Werner, S.; Groppe, S.; Pionteck, T.

In: 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, 2016, 10.1109/ReConFig.2015.7393300

Book chapter

An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases

Blochwitz, C.; Joseph, J.M.; Backasch, R.; Pionteck, T.; Werner, S.; Heinrich, D.; Groppe, S.

In: 2015 International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, 2016, 10.1109/ReConFig.2015.7393291

Book chapter

Adaptive allocation of default router paths in Network-on-Chips for latency reduction

Joseph, Jan Moritz; Blochwitz, Christioher; Pionteck, Thilo

In: Proceedings of the 2016 International Conference on High Performance Computing & Simulation (HPCS 2016): July 18-22, 2016, Innsbruck, Austria - Piscataway, NJ: IEEE[Kongress: 2016 International Conference on High Performance Computing & Simulation (HPCS), Innsbruck, Austria, 18-22 July, 2016]

Book chapter

Hardware-accelerated pose estimation for embedded systems using vivado HLS

Joseph, Jan Moritz; Winker, Tobias; Ehlers, Christian; Blochwitz, Christopher; Pionteck, Thilo

In: ReConFig: 2016 International Conference on Reconfigurable Computing and FPGAs : November 30 - December 2, Cancun, Mexico - Piscataway, NJ: IEEE[Kongress: 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig, Cancun, Mexico, November 30 - December 2, 2016]

Peer-reviewed journal article

Runtime adaptive hybrid query engine based on FPGAs

Werner, Stefan; Heinrich, Dennis; Groppe, Sven; Blochwitz, Christopher; Pionteck, Thilo

In: Open journal of databases: OJDB - Lübeck: RonPub UG, Bd. 3.2016, 1, S. 21-41

Editor

Architecture of Computing Systems – ARCS 2016

Hannig, Frank; Cardoso, João M. P.; Pionteck, Thilo; Fey, Dietmar; Schröder-Preikschat, Wolfgang; Teich, Jürgen

In: 2016

2015

Book chapter

Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs

Joseph, J.M.; Blochwitz, C.; Pionteck, T.; Garcia-Ortiz, A.

In: 2015 Nordic Circuits and Systems Conference, NORCAS 2015: NORCHIP and International Symposium on System-on-Chip, SoC 2015, 2015, 10.1109/NORCHIP.2015.7364370

Book chapter

Automated composition and execution of hardware-Accelerated operator graphs

Werner, S.S.; Heinrich, D.; Piper, J.; Groppe, S.; Backasch, R.; Blochwitz, C.; Pionteck, T.

In: 10th International Symposium on Reconfigurable and Communication-centric Systems-on-Chip, ReCoSoC 2015, 2015, 10.1109/ReCoSoC.2015.7238078

Book chapter

Hybrid FPGA approach for a B+ tree in a Semantic Web database system

Heinrich, D.; Werner, S.; Stelzner, M.; Blochwitz, C.; Pionteck, T.; Groppe, S.T.

In: 10th International Symposium on Reconfigurable and Communication-centric Systems-on-Chip, ReCoSoC 2015, 2015, 10.1109/ReCoSoC.2015.7238093

Peer-reviewed journal article

RAW 2014: Random number generators on FPGAS

Raitza, M.; Vogt, M.; Hochberger, C.; Pionteck, T.

In: ACM Transactions on Reconfigurable Technology and Systems, Vol. 9, 2015, Issue 2, 10.1145/2807699

2014

Book chapter

Parallel and pipelined filter operator for hardware-accelerated operator graphs in semantic web databases

Werner, S.; Heinrich, D.; Stelzner, M.; Groppe, S.; Backasch, R.; Pionteck, T.

In: Proceedings - 2014 IEEE International Conference on Computer and Information Technology, CIT 2014, 2014, S. 539-546, 10.1109/CIT.2014.162

Book chapter

Influence of magnetic fields and X-radiation on ring oscillators in FPGAs

Raitza, M.; Vogt, M.; Hochberger, C.; Pionteck, T.

In: Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS, 2014, S. 199-204, 10.1109/IPDPSW.2014.26

Book chapter

A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling

Joseph, J.M.; Pionteck, T.

In: 2014 International Symposium on System-on-Chip, SoC 2014, 2014, 10.1109/ISSOC.2014.6972440

Book chapter

Identifying homogenous reconfigurable regions in heterogeneous FPGAs for module relocation

Backasch, R.; Hempel, G.; Werner, S.; Groppe, S.; Pionteck, T.

In: 2014 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2014, 2014, 10.1109/ReConFig.2014.7032533

2013

Book chapter

Hardware-accelerated join processing in large Semantic Web databases with FPGAs

Werner, S.; Groppe, S.; Linnemann, V.; Pionteck, T.

In: Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013, 2013, S. 131-138, 10.1109/HPCSim.2013.6641403

Book chapter

Prioritizing semi-static data streams in network-on-chips for runtime reconfigurable systems

Pionteck, T.; Osterloh, C.

In: Proceedings of the 2013 International Conference on High Performance Computing and Simulation, HPCS 2013, 2013, S. 229-232, 10.1109/HPCSim.2013.6641419

Book chapter

Register allocation for high-level synthesis of hardware accelerators targeting FPGAs

Hempel, G.; Hoyer, J.; Pionteck, T.; Hochberger, C.

In: 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2013, 2013, 10.1109/ReCoSoC.2013.6581522

2012

Book chapter

An approach for performance estimation of hybrid systems with FPGAs and GPUs as coprocessors

Hampel, V.; Pionteck, T.; Maehle, E.

In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 7179 LNCS, 2012, S. 160-171, 10.1007/978-3-642-28293-5_14

2011

Book chapter

Linking formal description and simulation of runtime reconfigurable systems

Pionteck, T.; Osterloh, C.; Albrecht, C.

In: Proceedings - 2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, 2011, S. 158-163, 10.1109/ReConFig.2011.55

2010

Book chapter

Optimizing runtime reconfiguration decisions

Pionteck, T.; Sammann, S.; Albrecht, C.

In: Proceedings - IEEE/IFIP International Conference on Embedded and Ubiquitous Computing, EUC 2010, 2010, S. 39-46, 10.1109/EUC.2010.16

Book chapter

Latency reduction of selected data streams in network-on-chips for adaptive manycore systems

Pionteck, T.; Osterloh, C.; Albrecht, C.

In: 28th Norchip Conference, NORCHIP 2010, 2010, 10.1109/NORCHIP.2010.5669432

Book chapter

A concept of a trust management architecture to increase the robustness of nano age devices

Pionteck, T.; Brockmann, W.

In: Proceedings of the International Conference on Dependable Systems and Networks, 2010, S. 142-147, 10.1109/DSNW.2010.5542604

Editor

DynaCORE-dynamically reconfigurable coprocessor for network processors

Albrecht, C.; Foag, J.; Koch, R.; Maehle, E.; Pionteck, T.

In: Dynamically Reconfigurable Systems: Architectures, Design Methods and Applications, 2010, S. 335-354, 10.1007/978-90-481-3485-4_16

2009

Book chapter

On the impact of buffer size on packet loss in adaptable network-on-chips for runtime reconfigurable system-on-chips

Albrecht, C.; Koch, R.; Pionteck, T.

In: 2009 NORCHIP, 2009, 10.1109/NORCHP.2009.5397798

2008

Book chapter

On the design parameters of runtime reconfigurable systems

Pionteck, T.; Albrecht, C.; Koch, R.; Maehle, E.

In: Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL, 2008, S. 683-686, 10.1109/FPL.2008.4630039

Book chapter

SPP1148 booth: Network processors

Pionteck, T.; Koch, R.; Albrecht, C.; Maehle, E.; Meitinger, M.; Ohlendorf, R.; Wild, T.; Herkersdorf, A.

In: Proceedings - 2008 International Conference on Field Programmable Logic and Applications, FPL, 2008, S. 352, 10.1109/FPL.2008.4629960

Book chapter

An application-oriented synthetic network traffic generator

Albrecht, C.; Osterloh, C.; Pionteck, T.; Koch, R.; Maehle, E.

In: Proceedings - 22nd European Conference on Modelling and Simulation, ECMS 2008, 2008, S. 299-305

Book chapter

WCET determination tool for embedded systems software

Albrecht, C.; Koch, R.; Pionteck, T.; Maehle, E.; Werner, M.; Fuchsen, R.

In: SIMUTools 2008 - 1st International ICST Conference on Simulation Tools and Techniques for Communications, Networks and Systems, 2008, 10.4108/ICST.SIMUTOOLS2008.3044

Book chapter

Performance analysis of bus-based interconnects for a run-time reconfigurable co-processor platform

Albrecht, C.; Roß, P.; Koch, R.; Pionteck, T.; Maehle, E.

In: Proceedings of the 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing, PDP 2008, 2008, S. 200-205, 10.1109/PDP.2008.52

Book chapter

Design and simulation of runtime reconfigurable systems

Pionteck, T.; Albrecht, C.; Koch, R.; Brix, T.; Maehle, E.

In: Proceedings - 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS, 2008, S. 154-157, 10.1109/DDECS.2008.4538776

Peer-reviewed journal article

Adaptive communication architectures for runtime reconfigurable system-on-chips

Pionteck, T.; Albrecht, C.; Koch, R.; Maehle, E.

In: Parallel Processing Letters, Vol. 18, 2008, Issue 2, S. 275-289, 10.1142/S0129626408003387

2007

Book chapter

Communication architectures for dynamically reconfigurable FPGA designs

Pionteck, T.; Albrecht, C.; Koch, R.; Maehle, E.; Hübner, M.; Becker, J.

In: Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM, 2007, 10.1109/IPDPS.2007.370364

Book chapter

On the design of a dynamically reconfigurable function-unit for error detection and correction

Pionteck, T.; Stiefmeier, T.; Staake, T.; Glesner, M.

In: IFIP International Federation for Information Processing, Vol. 240, 2007, S. 283-297, 10.1007/978-0-387-73661-7_18

Book chapter

Teaching informatics students the secrets of hardware design

Pionteck, T.

In: Proceedings - MSE 2007: 2007 IEEE International Conference on Microelectronic Systems Education: Educating Systems Designers for the Global Economy and a Secure World, 2007, S. 31-32, 10.1109/MSE.2007.82

Book chapter

A lightweight framework for runtime reconfigurable system prototyping

Koch, R.; Pionteck, T.; Albrecht, C.; Maehle, E.

In: Proceedings of the International Workshop on Rapid System Prototyping, 2007, S. 61-64, 10.1109/RSP.2007.7

Book chapter

Modelling tile-based run-time reconfigurable systems using SystemC

Albrecht, C.; Pionteck, T.; Koch, R.; Maehle, E.

In: 21st European Conference on Modelling and Simulation: Simulations in United Europe, ECMS 2007, 2007, S. 509-514

2006

Book chapter

Applying partial reconfiguration to networks-on-chips

Pionteck, T.; Koch, R.; Albrecht, C.

In: Proceedings - 2006 International Conference on Field Programmable Logic and Applications, FPL, 2006, S. 155-160, 10.1109/FPL.2006.311208

Book chapter

An adaptive system-on-chip for network applications

Koch, R.; Pionteck, T.; Albrecht, C.; Maehle, E.

In: 20th International Parallel and Distributed Processing Symposium, IPDPS 2006, Vol. 2006, 2006, 10.1109/IPDPS.2006.1639445

Book chapter

A dynamically reconfigurable packet-switched network-on-chip

Pionteck, T.; Albrecht, C.; Koch, R.

In: Proceedings -Design, Automation and Test in Europe, DATE, Vol. 1, 2006

Peer-reviewed journal article

Exploring the capabilities of reconfigurable hardware for OFDM-based wlans

Pionteck, T.; Kabulepa, L.D.; Glesner, M.

In: IFIP International Federation for Information Processing, Vol. 200, 2006, S. 149-164, 10.1007/0-387-33403-3_10

2005

Book chapter

Reconfigurable embedded systems: An application-oriented perspective on architectures and design techniques

Glesner, M.; Hinkelmann, H.; Hollstein, T.; Indrusiak, L.S.; Murgan, T.; Obeid, A.M.; Petrov, M.; Pionteck, T.; Zipf, P.

In: Lecture Notes in Computer Science, Vol. 3553, 2005, S. 12-21

2004

Book chapter

Design of a reconfigurable AES encryption/decryption engine for mobile terminals

Pionteck, T.; Staake, T.; Stiefmeier, T.; Kabulepa, L.D.; Glesner, M.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 2, 2004, S. II545-II548

Book chapter

Reconfigurable platforms for ubiquitous computing

Glesner, M.; Hollstein, T.; Indrusiak, L.S.; Zipf, P.; Pionteck, T.; Petrov, M.; Zimmer, H.; Murgan, T.

In: 2004 Computing Frontiers Conference, 2004, S. 377-389

Book chapter

A dynamically reconfigurable function-unit for error detection and correction in mobile terminals

Pionteck, T.; Stiefmeier, T.; Staake, T.R.; Glesner, M.

In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 3203, 2004, S. 1090-1092

2003

Book chapter

Hardware evaluation of low power communication mechanisms for transport-triggered architectures

Pionteck, T.; García, A.; Kabulepa, L.D.; Glesner, M.

In: Proceedings of the International Workshop on Rapid System Prototyping, Vol. 2003-January, 2003, S. 141-147, 10.1109/IWRSP.2003.1207041

Book chapter

Reconfiguration requirements for high speed wireless communication systems

Pionteck, T.; Kabulepa, L.D.; Schlachta, C.; Glesner, M.

In: Proceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003, 2003, S. 118-125, 10.1109/FPT.2003.1275739

Peer-reviewed journal article

On the Rapid Prototyping of Equalizers for OFDM Systems

Pionteck, T.; Kabulepa, L.D.; Glesner, M.

In: Design Automation for Embedded Systems, Vol. 8, 2003, Issue 4, S. 283-295, 10.1023/B:DAEM.0000013063.88613.e0

2002

Book chapter

A framework for teaching (re)configurable architectures in student projects

Pionteck, T.; Zipf, P.; Kabulepa, L.D.; Glesner, M.

In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 2438 LNCS, 2002, S. 444-451

Book chapter

On the rapid prototyping of equalizers for OFDM systems

Pionteck, T.; Toender, N.; Kabulepa, L.D.; Glesner, M.; Kella, T.

In: Proceedings of the International Workshop on Rapid System Prototyping, Vol. 2002-January, 2002, S. 48-52, 10.1109/IWRSP.2002.1029737

2001

Book chapter

On the numerical accuracy of cordic-based frequency offset compensation in burst oriented OFDM systems

Kabulepa, L.D.; Kella, T.; Pionteck, T.; Ludewig, R.; Becker, J.; Plechinger, J.; Glesner, M.

In: Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, Vol. 2, 2001, S. 1069-1072

Book chapter

Efficient mapping of pre-synthesized IP-cores onto dynamically reconfigurable array architectures

Becker, J.; Liebau, N.; Pionteck, T.; Glesner, M.

In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 2147, 2001, S. 584-589

Book chapter

Design and implementation of a coarse-grained dynamically reconfigurable hardware architecture

Becker, J.; Pionteck, T.; Habermann, C.; Glesner, M.

In: Proceedings - IEEE Computer Society Workshop on VLSI, WVLSI 2001, 2001, S. 41-46, 10.1109/IWV.2001.923138

Editor

Effiziente IP-basierte abbildungsverfahren für dynamisch rekonfigurierbare array-architekturen

Becker, J.; Pionteck, T.; Glesner, M.

In: ITG-Fachbericht, 2001, Issue 164, S. 315

2000

Book chapter

DReAM: A dynamically reconfigurable architecture for future mobile communication applications

Becker, J.; Pionteck, T.; Glesne, M.

In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Vol. 1896, 2000, S. 312-321

Book chapter

An application-tailored dynamically reconfigurable hardware architecture for digital baseband processing

Becker, J.; Pionteck, T.; Glesner, M.

In: Proceedings - 13th Symposium on Integrated Circuits and Systems Design, 2000, S. 341-346, 10.1109/SBCCI.2000.876052

Cooperations
  • Georgia Tech, School of Electrical and Computer Engineering, Atlanta
  • Otto-von-Guericke-Univeristät Magdeburg, Prof. Gunter Saake
  • Privatdozent Dr. Sven Groppe, Universität zu Lübeck
  • Universität Bremen, Prof. Alberto Garcia-Ortiz
  • Universität zu Lübeck, Institut für Informationssysteme
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